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TBGenerator - program for testing and diagnosting HDL designs (Verilog or VHDL).
This
program reads source files (VHDL or Verilog) and automatically
generates test bench file (Verilog or VHDL format) for the selected
module and macro file (Tcl/Tk, Sh) for particular simulator (ModelSim,
Active-HDL/Riviera, NC-sim, VCSi and others). You don't have to waste
your time for writing test benches!
You can define input stimulus for in/inout ports either by
the formula, by the clock pulse, by random variable or you can define
an input file with stimulus data (text file with input vectors and
time). You can change only the stimulus in the input file without
changing the test bench file. The values of all the ports will be
written to the file during the simulation if you chose to do so. You
can see the wave form of testing module in future.
Program has some additional tools:
- generator of components declaration for chosen module;
- frequency to time converter and vice versa;
- input file editor new;
- wave form new.
New GUI. User-friendly interface and advanced help.
This program is shareware with a trial period 30 days. |
